1. FIELD OF THE INVENTION
The present invention is generally directed to semiconductor devices and processing, and, more particularly, to a novel semiconductor device having an enhanced width dimension and a method of making same.
2. DESCRIPTION OF THE RELATED ART
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, the size of many components of a typical field effect transistor, e.g., channel length, source/drain junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, FIG. 1 and FIG. 2 depict an illustrative transistor 10 for purposes of explaining one or more problems that may be solved or reduced by the present invention. FIG. 1 is a cross-sectional front view of the transistor 10 showing the channel length or transistor length xe2x80x9cL.xe2x80x9d FIG. 2 is a cross-sectional side view of the transistor 10 shown in FIG. 1 taken along the line xe2x80x9c2xe2x80x942,xe2x80x9d i.e., showing the transistor width xe2x80x9cW.xe2x80x9d As shown in FIG. 1, the transistor 10 is formed in an active area 12 that is defined in a semiconducting substrate 14 by an isolation structure 16 formed therein. The transistor 10 is comprised of a gate insulation layer 18, a gate electrode 20, a sidewall spacer 24, and a plurality of source/drain regions 28. The transistor 10 is also comprised of metal silicide layers 29 formed above the source/drain regions 28 and the gate electrode 20.
All of the various components of the transistor 10 depicted in FIG. 1 may be formed using a variety of known processing techniques, and they may be comprised of a variety of materials. For example, the gate insulation layer 18 may be comprised of a thermally grown layer of silicon dioxide, the gate electrode 20 may be comprised of polysilicon, the sidewall spacer 24 may be comprised of silicon dioxide, and the metal silicide regions 29 may be comprised of, for example, cobalt silicide or titanium silicide. The isolation structure 16 is typically comprised of an insulating material, such as silicon dioxide, or other like material. The isolation structure 16 may be constructed by forming a trench 17 in the substrate 14, filling the trench with an appropriate insulating material, e.g., silicon dioxide, and, thereafter, performing a chemical mechanical polishing operation to remove any excess material.
In designing modern integrated circuit devices, one parameter of a transistor that is of particular importance is known as its drive current. Stated simply, the drive current of a transistor is the amount of current flowing from the drain region to the source region of a transistor. All other things being equal, it is desirable that transistors have as large a drive current as possible without otherwise adversely impacting the performance of the transistor, i.e., without generating excessive heat or excessive off-state leakage currents, etc.
The drive current of the device may be increased by reducing the channel length of the transistor. However, all other things being equal, the smaller the channel length of the transistor, the greater the off-state leakage current. Moreover, the off-state leakage current increases exponentially as the channel length of the device decreases. Off-state leakage currents also increase as the transistor width increases, but at a rate that is less than the exponential rate associated with reductions in the channel length of a device. Thus, in attempting to increase the drive current of a transistor, increasing the width of the transistor results in lower off-state leakage currents, as compared to increasing the drive current the same amount by reducing the channel length. Moreover, to a great extent, reducing the channel length of the device is limited by available photolithography and etching processes.
Typically, the amount of drive current that can be generated per unit width (xe2x80x9cwxe2x80x9d) of the transistor is a known value. Thus, when a total drive current is desired or required for a particular circuit application, the required width of the transistor to accomplish this purpose may be readily determined. Thus, for a given type of transistor, an application requiring a transistor having a width of 30 w may be satisfied by a single transistor having a width of approximately 30 w or six transistors, arranged in parallel, each having a width of approximately 5 w. Using this process, the layout of integrated circuit devices across the surface of a portion of a semiconducting substrate is accomplished, with the ultimate goal being to minimize consumption of wafer plot space, i.e., to maximize the use of available substrate. Thus, it would be desirable to have a transistor in which the width dimension of a substrate can be maximized in a given plot space of semiconducting substrate.
The present invention is directed to a method that solves or reduces some or all of the aforementioned problems.
The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.
In one illustrative embodiment, the method of making a transistor comprises providing a semiconducting substrate, forming a recessed isolation structure in a trench formed in the substrate, the recessed isolation structure thereby defining a recess in the substrate, forming a gate insulation layer and a gate electrode above the substrate, a portion of the gate insulation layer and gate electrode extending into the recess in the substrate and above the recessed isolation structure, and forming a plurality of source/drain regions in the substrate adjacent the gate electrode.